Get startedKey Responsibilities: Architecture: Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL…
Key Responsibilities: PDK Download & Setup – Download, install, and configure Process Design Kits (PDKs) for analog/mixed-signal design environments.
Key Responsibilities Develop and implement innovative DFT IP and features to support ATE, in-system test, debug, and diagnostics.
We are looking for an engineer who can own the intersection of design quality, automation, and design integration.
Key Responsibilities Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G) Develop micro-architecture specifications and implement…
Qualification: Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields 10+ years of experience in DSP system architecture and algorithm development for…
Key Responsibilities: Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based…
Key Responsibilities: Architecture & RTL Design Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff Design data path and clocking…
Key Responsibilities: Develop and execute verification plans for connectivity IPs and Chiplets Create and maintain SystemVerilog/UVM-based verification environments Write and…
Key Responsibilities: Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces…
Key Responsibilities: Provide technical verification leadership to Eliyan products and provide guidance to junior engineers.
Key Responsibilities: Develop and execute RNM AMS model for best in class PHYs. Make sure the quality of models reflects schemetics.
Key Responsibilities: Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
Eliyan is building NuLink, a proprietary die-to-die chiplet interconnect fabric purpose-built for AI infrastructure at hyperscale.
What we are looking for: Strong analytical mindset with expertise across multiple physics domains (thermal, electrical, mechanical) Excellent communication skills to present…
Key Responsibilities Working closely with analog circuit designers to understand and define IO requirements co-designed with the channel Responsible for pre-layout and post layout…
Responsibilities: Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.
Responsibilities: Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraints Well defined boundaries with lego…
As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products.
As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products.
We're looking for a hands-on validation and characterization engineer working at the intersection of photonics, opto-electronics, and high-speed electrical interconnect.
Key Responsibilities: Program Leadership: Own end-to-end execution of IP, ASIC, and platform programs, from architecture and IP definition through design, verification…
As a Principal Technical Program Manager, you will own the schedule, risk, and cross-team strategy for our packaging and SI/PI program portfolio, translating between analog and…
Key Responsibilities: * Execute early silicon bring-up activities, including system initialization, validation infrastructure development, and test content creation for high-speed…